{"id":196,"date":"2010-04-26T14:04:55","date_gmt":"2010-04-26T05:04:55","guid":{"rendered":"http:\/\/leaqua.mulple.com\/?p=196"},"modified":"2018-03-15T10:38:14","modified_gmt":"2018-03-15T01:38:14","slug":"atmega128%ec%97%90%ec%84%9c-%ed%83%80%ec%9d%b4%eb%a8%b8%ec%b9%b4%ec%9a%b4%ed%84%b0-%ec%82%ac%ec%9a%a9%ec%9d%84-%ec%9c%84%ed%95%9c-%ec%b4%88%ea%b8%b0%ec%b9%98-%ec%85%8b%ed%8c%85%ed%95%98%eb%8a%94","status":"publish","type":"post","link":"https:\/\/leaqua.mulple.com\/?p=196","title":{"rendered":"atmega128\uc5d0\uc11c \ud0c0\uc774\uba38\/\uce74\uc6b4\ud130 \uc0ac\uc6a9\uc744 \uc704\ud55c \ucd08\uae30\uce58 \uc14b\ud305\ud558\ub294\ubc95"},"content":{"rendered":"

\"\"<\/span><\/span><\/p>\n

\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 1msec<\/span><\/span><\/p>\n

\/\/ X-TAL<\/span>\ud074\ub7ed \/ TCCR0<\/span>\ubd84\uc8fc\ube44 \/ TCNT0<\/span>\ud0c0\uc774\uba38\uac12 = \uc8fc\ud30c\uc218, \uc5ed\uc218\ub97c \ucde8\ud558\uba74 \uc2dc\uac04 \/\/16000000Hz<\/span>\/128\/125=1000Hz<\/span>, (256-125)=131<\/span><\/span><\/p>\n

TCCR0=5<\/span>; TCNT0=131<\/span>; TIMSK=1<\/span>; <\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 5msec \/\/16000000Hz<\/span>\/1024\/78=200.32Hz<\/span>, (256-78)=178<\/span><\/span><\/span><\/p>\n

TCCR0<\/span>=7<\/span>; TCNT0<\/span>=178<\/span>; TIMSK<\/span>=1<\/span>;<\/span><\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 10msec \/\/16000000Hz<\/span>\/1024\/156=100.16Hz<\/span>, (256-156)=100<\/span><\/span><\/span><\/p>\n

TCCR0<\/span>=7<\/span>; TCNT0<\/span>=100<\/span>; TIMSK<\/span>=1<\/span>; <\/span><\/span><\/p>\n

 <\/p>\n

1msec\ub294 \ubd84\uc8fc\ube44 128\uc744 \uc0ac\uc6a9\ud574\uc11c \uc815\ud655\ud55c 1msec\ub97c \ub9cc\ub4e4\uc5c8\uc9c0\ub9cc<\/span><\/span><\/p>\n

8\ube44\ud2b8 \ud0c0\uc774\uba38\ub85c\ub294 \ub354 \uae34 \uc2dc\uac04\uc744 \ub9cc\ub4e4 \uc218 \uc5c6\uc73c\ubbc0\ub85c<\/span><\/span><\/p>\n

\uc624\ucc28\uac00 \uc788\ub354\ub77c\ub3c4 1024\ub97c \uc0ac\uc6a9 \ud588\uc2b5\ub2c8\ub2e4.<\/span><\/span><\/p>\n

 <\/p>\n

8\ube44\ud2b8 \ud0c0\uc774\uba380\ub85c \ub9cc\ub4e4 \uc218 \uc788\ub294 \uc2dc\uac04 \ubc94\uc704\ub294 \uc5ec\uae30\uae4c\uc9c0\uc774\uba70<\/span><\/p>\n

\ub354 \uae34 50msec \uc640 100msec\ub294<\/span><\/p>\n

\ud0c0\uc774\uba38 \uc778\ud130\ub7fd\ud2b8 \ud568\uc218 \ub0b4\uc5d0\uc11c \uc0ac\uc6a9\uc790 \ubcc0\uc218\ub85c \ucc98\ub9ac \ud558\uba74 \ub429\ub2c8\ub2e4.<\/span><\/p>\n

 <\/p>\n

 <\/p>\n

int count=0;<\/span><\/p>\n

 <\/p>\n

ISR(TIMER0_OVF_vect){ \/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 1msec<\/span><\/span><\/p>\n

\/\/<\/span> interrupt

\n\t\t\t\t\t
\n\t\t\t\t\t\t[TIM0_OVF] void timer0_ovf_isr(void){ \/\/ \ucf54\ub4dc\ube44\uc83c\uc6a9<\/span><\/span><\/p>\n

\u00a0\u00a0\u00a0 count++;<\/span><\/p>\n

\u00a0\u00a0\u00a0 if(count==50<\/span>){ count=0<\/span>; } \/\/ 50<\/span>msec<\/span><\/span><\/p>\n

}<\/span><\/p>\n

 <\/p>\n

ISR(TIMER0_OVF_vect){ \/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 1msec<\/span><\/span><\/p>\n

\/\/<\/span> interrupt [TIM0_OVF] void timer0_ovf_isr(void){ \/\/ \ucf54\ub4dc\ube44\uc83c\uc6a9<\/span><\/span><\/span><\/p>\n

\u00a0\u00a0\u00a0 count++;<\/span><\/p>\n

\u00a0\u00a0\u00a0 if(count==100<\/span>){ count=0<\/span>; } \/\/ 100<\/span>msec<\/span><\/span><\/p>\n

}<\/span><\/p>\n

 <\/p>\n

5msec\uc640\u00a0 10msec\ub3c4 \uc0ac\uc6a9\uc790 \ubcc0\uc218\uc778 count<\/span>\ub85c \ub9cc\ub4e4 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/span><\/p>\n

 <\/p>\n

 <\/p>\n

 <\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba381 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 1msec \/\/ X-TAL<\/span>\ud074\ub7ed \/ TCCR1B<\/span>\ubd84\uc8fc\ube44 \/ TCNT1<\/span>\ud0c0\uc774\uba38\uac12 = \uc8fc\ud30c\uc218, \uc5ed\uc218\ub97c \ucde8\ud558\uba74 \uc2dc\uac04 \/\/ \ud074\ub7ed \/ \ubd84\uc8fc\ube44 \/ \ud0c0\uc774\uba38\uac12 = \ud0c0\uc774\uba38 \uc778\ud130\ub7fd\ud2b8 \uc8fc\ud30c\uc218, \uc5ed\uc218\ub97c \ucde8\ud558\uba74 \uc2dc\uac04 \/\/16000000Hz<\/span>\/64\/250=1000Hz<\/span>,(65536-250)=65286 <\/span><\/span><\/span><\/p>\n

TCCR1B<\/span>=3<\/span>; TCNT1<\/span>=65286<\/span>; TIMSK<\/span>=4<\/span>;<\/span><\/span><\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba381 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 5msec \/\/16000000Hz<\/span>\/64\/1250=200Hz<\/span>,(65536-1250)=64286 <\/span><\/span><\/span><\/p>\n

TCCR1B<\/span>=3<\/span>; TCNT1<\/span>=64286<\/span>; TIMSK<\/span>=4<\/span>;<\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba381 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 10msec \/\/16000000Hz<\/span>\/64\/2500=100Hz<\/span>,(65536-2500)=63036<\/span><\/span><\/span><\/p>\n

TCCR1B<\/span>=3<\/span>; TCNT1<\/span>=63036<\/span>; TIMSK<\/span>=4<\/span>;<\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba381 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 50msec \/\/16000000Hz<\/span>\/64\/12500=20Hz<\/span>,(65536-12500)=53036 <\/span><\/span><\/span><\/p>\n

TCCR1B<\/span>=3<\/span>; TCNT1<\/span>=53036<\/span>; TIMSK<\/span>=4<\/span>;<\/span><\/p>\n

 <\/p>\n

\/\/ \ud0c0\uc774\uba381 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 100msec \/\/16000000Hz<\/span>\/64\/25000=10Hz<\/span>,(65536-25000)=40536<\/span><\/span><\/span><\/p>\n

TCCR1B<\/span>=3<\/span>; TCNT1<\/span>=40536<\/span>; TIMSK<\/span>=4<\/span>;<\/span><\/p>\n

 <\/p>\n

 <\/p>\n

\/\/---------------------------------------------------- \r\n\/\/ mega128 timer1 interrupt test \r\n\/\/ xtal: 16MHZ\r\n\/\/---------------------------------------------------- \r\n#include <mega128.h> \r\n\/\/---------------------------------------------------- \r\nchar tmrCnt, tmr100ms, tmr500ms;\r\n\r\n\/\/---------------------------------------------------- \r\n\r\nvoid init_timer()\r\n\r\n{ \r\n\r\n   TCNT1=0xfec7;  \/\/20ms(65536-313)\r\n   \/\/TCNT1=0xfe79; \/\/25ms(65536-391)\r\n   \/\/TCNT1=0xfd8f; \/\/40ms(65536-625)\r\n   \/\/TCNT1=0xfcf2; \/\/50ms(65536-782)\r\n   \/\/TCNT1=0xfc58; \/\/60ms(65536-936)\r\n   \/\/-----16bit max timer\r\n   \/\/ 1\/16(MHZ)=0.0625\r\n   \/\/ 0.0625*1024(prescaler:5)=64\r\n   \/\/ 64*65536(16bit)=4,194,304\r\n   \/\/ 4.194304 sec\r\n   \/\/------------\r\n   \/\/ ex1) TCCR1B=5(1024), xtal:16MHz, per2ms?\r\n   \/\/      1\/16=0.0625\r\n   \/\/      0.0625*1024=64\r\n   \/\/      2,000\/64=31\r\n   \/\/      65,536-31=65,505-->hex:ffe1\r\n   \/\/      TCNT1=0xffe1;\r\n   \/\/------------\r\n   \/\/ ex2) TCCR1B=5(1024), xtal:16MHz, per5ms?\r\n   \/\/      1\/16=0.0625\r\n   \/\/      0.0625*1024=64\r\n   \/\/      5,000\/64=78\r\n   \/\/      65,536-78=65,457-->hex:ffb1\r\n   \/\/      TCNT1=0xffb1;\r\n   \/\/------------\r\n   \/\/ ex3) TCCR1B=5(1024), xtal:16MHz, per50ms?\r\n   \/\/      1\/16=0.0625\r\n   \/\/      0.0625*1024=64\r\n   \/\/      50,000\/64=781\r\n   \/\/      65,536-781=64,755-->hex:fcf3\r\n   \/\/      TCNT1=0xfcf3;\r\n   \/\/------------\r\n   \/\/ ex4) TCCR1B=5(1024), xtal:16MHz, per500ms?\r\n   \/\/      1\/16=0.0625\r\n   \/\/      0.0625*1024=64\r\n   \/\/      500,000\/64=7,812\r\n   \/\/      65,536-7,812=57,724-->hex:e17c\r\n   \/\/      TCNT1=0xe17c;\r\n   \/\/------------\r\n   \/\/ ex5) TCCR1B=5(1024), xtal:16MHz, per1sec?\r\n   \/\/      1\/16=0.0625\r\n   \/\/      0.0625*1024=64\r\n   \/\/      1,000,000\/64=15,625\r\n   \/\/      65,536-15,625=49,911-->hex:c2f7\r\n   \/\/      TCNT1=0xc2f7;\r\n   \/\/------------\r\n   \/\/ ex6) TCCR1B=3(64), xtal:8MHz, per10ms?\r\n   \/\/      1\/8=0.125\r\n   \/\/      0.125*64=8\r\n   \/\/      10,000\/8=1,250\r\n   \/\/      65,536-1,250=64,286-->hex:fb1e\r\n   \/\/      TCNT1=0xfb1e;\r\n   \/\/------------\r\n}\r\n\/\/----------------------------------------------------\r\ninterrupt [TIM1_OVF] void timer1_ovf_isr()\r\n{\r\n   init_timer();\r\n   \/\/----------------per25ms\r\n   PORTD.0=~PORTD.0; \/\/test pulse\r\n   \/\/----------------\r\n\/\/time_100ms:\r\n   if(++tmrCnt < 4) return; \/\/no 100ms?\r\n   \/\/----------------per100ms\r\n \r\n   \/\/----------------\r\n\/\/time_500ms:\r\n   tmrCnt=0;\r\n   if(++tmr100ms < 5) return; \/\/no 500ms?\r\n   \/\/----------------per500ms\r\n \r\n   \/\/----------------\r\n\/\/time_sec:\r\n   tmr100ms=0;\r\n   if(++tmr500ms & 1) return; \/\/no 1sec?\r\n   \/\/----------------per1sec\r\n \r\n   \/\/----------------\r\n} \r\n\/\/----------------------------------------------------\r\nvoid main()\r\n{\r\n   DDRD.0=1; \/\/out\r\n   TCCR1B=5; init_timer(); \/\/prescaler:1024(5)\r\n   TIMSK|=0x04; \/\/enable timer1 interrupt\r\n \r\n   #asm("sei") \/\/enable global interrupt\r\n   while(1);   \/\/endless loop\r\n}\r\n\/\/ -------------------- end of file -------------------   \r\n\r\n\r\n<\/pre>\n
<\/div>\n\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div><\/div><\/div><\/p>\n","protected":false},"excerpt":{"rendered":"
\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 1msec
\n\/\/ X-TAL\ud074\ub7ed \/ TCCR0\ubd84\uc8fc\ube44 \/ TCNT0\ud0c0\uc774\uba38\uac12 = \uc8fc\ud30c\uc218, \uc5ed\uc218\ub97c \ucde8\ud558\uba74 \uc2dc\uac04 \/\/16000000Hz\/128\/125=1000Hz, (256-125)=131
\nTCCR0=5; TCNT0=131; TIMSK=1;
\n 
\n\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 \uc778\ud130\ub7fd\ud2b8 5msec \/\/16000000Hz\/1024\/78=200.32Hz, (256-78)=178
\nTCCR0=7; TCNT0=178; TIMSK=1;
\n 
\n\/\/ \ud0c0\uc774\uba380 \uc624\ubc84\ud50c\ub85c\uc6b0 […]<\/p>\n","protected":false},"author":1,"featured_media":197,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0},"categories":[5],"tags":[54,48,39],"_links":{"self":[{"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/posts\/196"}],"collection":[{"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=196"}],"version-history":[{"count":5,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/posts\/196\/revisions"}],"predecessor-version":[{"id":1405,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/posts\/196\/revisions\/1405"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=\/wp\/v2\/media\/197"}],"wp:attachment":[{"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=196"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=196"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/leaqua.mulple.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=196"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}